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NCP1652, NCP1652A
di
V RCOMP +
@ T @ R CS @ A HF
N S L P @ 102.38k
R CS +
@
t on
V ref(PWM) + V RCOMP @
) V INST
R RCOMP + @ (eq. 24)
3.8 * 5.333 @ I PK @ R CS
3.8
R CS +
out @ t on
P
HF
(eq. 20)
dt primary
(eq. 21)
N P T @ A HF @ V out @ R RCOMP
At low line and full load, the output of the ac error
amplifier output is nearly saturated in a low state. While the
ac error amplifier output is saturated, I ACEA is zero and does
not contribute to the voltage across the internal 21.33 k W
resistor on the PWM comparator non-inverting input. In this
operation mode, the voltage across the 21.33 k W resistor is
determined solely by the ramp compensation and the
instantaneous switch current as given by Equation 22.
(eq. 22)
T
The voltage reference of the PWM Comparator,
V REF(PWM) , is 4 V. For these calculations, 3.8 V is used to
provide some margin. The maximum instantaneous switch
current voltage contribution, V INST , is given by
Equation 23.
V INST + I PK @ R CS @ A HF (eq. 23)
Substituting Equation 23 in Equation 22, setting
V REF(PWM) at 3.8 V (provides margin) and solving for
R RCOMP, Equation 24 is obtained.
102.38k t on
T
Replacing Equation 24 in Equation 21 we obtain:
(eq. 25)
N A @ V
N @ L ) 5.333 I PK
S P
latch is Set dominant which means that if both R and S are
high the S signal will dominate and Q will be high, which
will hold the power switch off.
The NCP1652 uses a pulse width modulation scheme
based on a fixed frequency oscillator. The oscillator
generates a voltage ramp as well as a pulse in sync with the
falling edge of the ramp. The pulse is an input to the PWM
Logic and Driver block. While the oscillator pulse is present,
the latch is reset, and the output drive is in its low state. On
the falling edge of the pulse, the OUTA goes high and the
power switch begins conduction.
The instantaneous inductor current is summed with a
current proportional to the ac error amplifier output voltage.
This complex waveform is compared to the 4 V reference
signal on the PWM comparator inverting input. When the
signal at the non-inverting input to the PWM comparator
exceeds 4 V, the output of the PWM comparator toggles to
a high state which drives the Set input of the latch and turns
the power switch off until the next clock cycle.
Brown ? Out
The NCP1652 incorporates a brown ? out detection circuit
to prevent the controller operate at low ac line voltages and
reduce stress in power components. A scaled version of the
rectified line voltage is applied to the VFF Pin by means of
a resistor divider. This voltage is used by the brown out
detector.
A brown ? out condition exists if the feedforward voltage
is below the brown ? out exit threshold, V BO(high) , typically
0.45 V. The brown ? out detector has 180 mV hysteresis. The
controller is enabled once V FF is above 0.63 V and V CC
reaches V CC(on) . OUTB is the last drive pulse. Figure 68
shows the relationship between the brown ? out, V CC , OUTA
and OUTB signals.
PWM Logic
The PWM and logic circuits are comprised of a PWM
comparator, an RS flip-flop (latch) and an OR gate. The
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